General Description
The THC63LVDF84B/THC63LVDF64B receiver sup-
ports wide VCC range(2.5~3.6V). At single 2.5V sup-
ply, the THC63LVDF84B/THC63LVDF64B reduces
EMI and power consumption.
The THC63LVDF84B receiver convert the four
LVDS(Low Voltage Differential Signaling) data streams
back into 28bits of CMOS/TTL data with falling edge
clock.
At a transmit clock frequency of 85MHz, 28bits of RGB
data and 4bits of LCD timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at
a rate of 2.3Gbps.
Also the THC63LVDF64B receiver convert the three
LVDS data streams back into 21bits of CMOS/TTL data
with falling edge clock.
At a transmit clock frequency of 85MHz, 21bits of RGB
data and 4bits of LCD timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at
a rate of 1.78Gbps
Features
- Wide VCC range: 2.5~3.6V
- Wide dot clock range: 20-85MHz suited for VGA,
SVGA, XGA and SXGA (VCC=3.0~3.6V)
- Wide dot clock range: 20-70MHz suited for VGA,
SVGA, XGA and SXGA (VCC=2.5V~3.6V)
- PLL requires No external components
- Rx power consumption < 80mW @VCC 2.5V,
65MHz Grayscale
- Power-Down Mode
- Low profile 56 Lead or 48 Lead TSSOP Package
- Pin compatible with THC63LVDF84A/F64A
